Input signals and power are provided to an integrated circuit from a semiconductor package (either flip-chip or wire-bond or package, flip chip package is our example for illustration here) through a series of bump pads. Capacitance associated with these bump pads is known to introduce significant discontinuities at a die-package interface. These discontinuities greatly degrade the system performance, so that even if the package and associated printed circuit board (PCB) are well-designed, the return loss of the system can be degraded by up to 10 decibels (dB) and the insertion loss up to 5 dB. If the system loss is large enough, the system loss can lead to possible system specification violations, and the overall system will not deliver the specified amount of performance.
Traditional methods used to mitigate the effect of the bump pad capacitance of the integrated circuit are often implemented either on the package or the printed circuit board. Methods implemented on the PCB generally rely on the use of long metal traces to dampen the amount of system return loss, in order to meet protocol return loss specification. At best, the use of long metal traces can be considered a work around methodology, as the metal traces introduce a large amount of attenuation to the system. Compensation methods on the package generally involve the use of an intrinsic package structure to reduce the amount of system loss. The on-package capacitive parasitics can be translated into inductive parasitics through a quarter wavelength transmission line, which as a result, balance the bump pad capacitance. A significant drawback of these methods is the compensation is effective in a narrow frequency band and is data rate dependent. In other words, the compensation from the methods described above is only effective over a small range of frequencies.
It is in this context that embodiments of the invention arise.